module alu(input [15:0] A,
           input [15:0] B,
           input [1:0] op_sel,
           output reg [15:0] out);

localparam BYPASS = 2'd0,
           ADD = 2'd1,
           SUB = 2'd2,
           NAND = 2'd3;

always @(*) begin
    out = 16'bz; //circuito aberto para evitar aparecimento de x.
    case(op_sel)
        BYPASS: out = A;
        ADD: out = B + A;
        SUB: out = B - A;
        NAND: out = ~(B & A);
    endcase
end
endmodule
        
